Engineer - RTL

Job Requirements

he RTL Design Engineer is responsible for designing and implementing digital circuits using Hardware Description Languages (HDL) such as Verilog or VHDL.They work on creating logic at the Register Transfer Level (RTL) and collaborate with verification, synthesis, and physical design teams.

Key Responsibilities

Understand and analyze design specifications / architecture documents.Develop RTL code using Verilog / SystemVerilog / VHDL.Perform functional simulations to verify design correctness.Work closely with verification, synthesis, and backend (physical design) teams.Debug design and simulation issues.Optimize RTL for area, timing, and power.Support integration of IP blocks at chip or subsystem level.Maintain documentation for design and test plans.

Required Skills

Good understanding of digital electronics and logic design.Hands-on experience or coursework in Verilog / SystemVerilog / VHDL.Knowledge of simulation tools (like ModelSim, QuestaSim, or VCS).Basic understanding of timing concepts, clocking, and resets.Familiarity with synthesis and lint checks is a plus.Problem-solving and debugging skills.

Qualification

B.E / B.Tech / M.E / M.Tech in Electronics / Communication / VLSI / Instrumentation. Coursework or projects in Digital Design, HDL coding, FPGA/ASIC design preferred.

Benefits

Required Skills:Good understanding of digital electronics and logic design.Hands-on experience or coursework in Verilog / SystemVerilog / VHDL.Knowledge of simulation tools (like ModelSim, QuestaSim, or VCS).Basic understanding of timing concepts, clocking, and resets.Familiarity with synthesis and lint checks is a plus.Problem-solving and debugging skill