Design Verification Engineer

• You will be part of the team verifying IPs and SoCs leading to first Si success.
• Manage and lead a team of Verification engineers
• IP verification is coverage driven using latest industry standard methodologies and HVLs.
• Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases.
• Code coverage, Functional coverage and assertions are desired.
• ARM based SoC verification experience is an added advantage.
• Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus.
• Multiple positions with emphasis on AMS and Power aware verification.
• Should have worked on GLS.

Key Responsibilities:

1. Lead Verification Efforts:

• Manage and mentor a team of IP and SoC verification engineers.
• Drive verification strategy to ensure first silicon success.

1. Verification Planning & Execution:

• Define test plans and verification methodologies using UVM/OVM.
• Develop and maintain reusable testbenches and test cases.

1. Coverage & Quality Assurance:

• Ensure high-quality verification through code coverage, functional coverage, and assertions.
• Perform Gate-Level Simulations (GLS) and Low Power Verification.

1. Collaboration & Communication:

• Work closely with design, architecture, and validation teams.
• Provide regular updates and technical guidance to stakeholders.

1. Tool & Script Development:

• Automate verification tasks using scripting languages like Python, Perl, Shell, and Tcl.
• Utilize industry-standard tools for emulation, LEC, and AMS verification.

Primary Skills:

• Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl.

Secondary Skills:

• Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR.