Associate III - VLSI - SCL

3 - 5 Years
1 Opening
Bangalore

Role Proficiency:

Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision

Outcomes:

Measures of Outcomes:

Outputs Expected:

Quality of the deliverables:

Timely delivery:

Team Work:

Innovation & Creativity:

Skill Examples:

Knowledge Examples:

• Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing
• Understanding of the technical specs and assigned tasks:
Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill


• Additional Comments:

  Job Title: Standard Cell Layout Engineer Location: [ Bangalore ] Experience: [2-8 Years] Job Description: Key Responsibilities: • Perform physical layout design of standard cells and library development to meet performance, area, and power targets. • Work closely with circuit designers to translate schematics into optimized layouts. • Perform floor planning, placement, routing, and device-level layout for standard cells ensuring adherence to design rules (DRC) and layout vs schematic (LVS) checks. • Optimize layouts for high density, performance, and manufacturability. • Conduct parasitic extraction and analysis to meet circuit performance requirements. • Support layout verification, QA, and signoff processes. Required Skills: • Strong knowledge of CMOS technology, layout techniques, and design rules. • Experience in standard cell layout development (basic logic gates, sequential cells, complex cells). • Proficiency in Cadence Virtuoso, Calibre, or similar layout and verification tools. • Good understanding of DRC, LVS, ERC, and parasitic extraction flows. • Ability to work collaboratively in a cross-functional environment with circuit designers and methodology teams. • Attention to detail, strong problem-solving skills, and ability to meet tight schedules. Preferred Qualifications: • Experience in advanced technology nodes (7nm / 5nm / 3nm). • Familiarity with layout automation techniques and scripting (SKILL, Perl, Python). • Exposure to EDA flow enhancements and layout methodologies. Education: • B.E./B.Tech/M.Tech in Electronics, Electrical, or VLSI Design.

Standard cell layout,Circuit Design,EDA Flow