Analog Layout engineer

5 - 7 years

25 - 27 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Description

Skill set required :
Should have a very good understanding of semiconductor and analog basics.
Good hands-on experience in toplevel integration and block level analog layouts like ADC/DAC/ PLL/high speed Serdes, Power Management blocks
Hands-on experience in 7nm, 5nm.N3E or lower node experience is a plus..
Good Experience with floor planning, matching, EM/IR and DFM issues and other analog layout related concepts and hands on implementation from scratch.
Experience of LVS, Density, lower node DRCs, Parasitic reduction and other lower node challenges. Good experience in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Avoid resumes only with Intel project exposure. TSMC/ Samsung/serdes projects are preferable to have in resumes. Analog Mixed signal verification experience. Understanding CMOS analog design like References, Amplifiers, Comparators, etc.. Running spice and cosim simulations for analog/AMS blocks like ADCs, PLLs etc.. Writing analog checker and running regression across operating conditions.Digital verification skill and strong knowledge on system verilog and UVM.

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