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Posted:2 months ago| Platform: 
Hybrid
Full Time
Required skill :Semiconductor Layout Development, CAD Tool Proficiency, Layout Verification, Standard Cell, Analog, Mixed-Signal, and Custom Digital Block Layouts Advanced CMOS Process, Layout Library Development, standard cell layout library developments. Physical Verification, Layout Optimization, Design Rules, Yield, and Reliability, Layout Fundamentals, Schematic Understanding, Layout Effects on Circuit, Cadence Virtuoso and Mentor Caliber Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques Problem-Solving: Excellent problem-solving skills in physical verification. Teamwork and Communication: Ability to work in a team and communicate effectively. Guiding junior team members
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