We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.

Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. KEY RESPONSIBILITIES: Verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate-level simulation, power-aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs . ACADEMIC CREDENTIALS: Require BS w/ 6+ yrs or MS w/ 4+ yrs or PhD w/ 2+ yrs in Electrical Engineering, Computer Engineering or Computer Science.

As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have minimum 8 to 15 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer/Electronics/Electrical Engineering

We are seeking a PCIe device developer with expertise in PCIe driver and Linux kernel development. The ideal candidate will work on our DPU and AINIC firmware - low-level system software, enabling hardware functionality, optimizing performance, and ensuring seamless integration between hardware and software layers. Key Responsibilities: - Develop PCIe driver/features for our AINIC and DPU product line - Optimize PCIe driver performance, including power management and low-latency data transfers - Work with kernel-level programming in Linux including experience with sysfs, procfs, and PCIe Subsystem - Debug and troubleshoot PCIe bus communication, DMA, interrupts, and memory mapping issues - Provide support for hot-plug and interrupt mechanisms - Collaborate with hardware team to understand PCIe components like serdes and bringup in software Required Skills & Experience: 10-15 years of experience in managing PCIe devices, Linux kernel programming, device driver development, and system software engineering. Proficiency in C programming for system-level software. Good understanding of PCIe enumeration, link training, device initialization sequence, configuration space handling, SR-IOV, bare-metal and hypervisor VM architectures Strong debugging and troubleshooting skills using kernel logs, GDB and other debugging tools. Experience in hardware bringup, bootloaders, and ARM architecture. Familiarity with Buildroot, or other embedded Linux systems. Knowledge of memory management, interrupts, and scheduling in Linux. Educational Qualifications: Bachelor s or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field.

AMD is looking for an influential software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess l eadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Develop technical relationships with peers and partne rs Develop and Drive execution of comprehensive, highly effective automation scripts for Test and Build Infrastructure Actively contribute to various other CICD practices Collaborate closely with multiple teams to deliver key solutions and the technology to support them Monitor and Maintain the health of the build jobs on a regular basis Triage the failures, Troubleshoot problems, raise bugs, follow-up with the concerned teams for timely resolution of issues PREFERRED EXPERIENCE: Minimum 7 years of industry experience in automation and programming Proficient in Python and ability to write clean and debuggable software Have worked on automation infrastructure Familiar with various testing methodologies preferably in networking domain Familiar with CI/CD tooling/frameworks, including but not limited to Jenkins / Bamboo / Travis-CI / Similar. Familiar with GitHub/GitLab/BitBucket/similar version control systems and webhook integrations. Can work on complex suite of infra code Well versed with writing test cases for code Good knowledge of infrastructure (servers eg boot, pxe, IPMI, APC, network e.g. switching/routing/automation) Proficient in Linux admin DESIRED EXPERIENCE: Although not mandatory, Knowledge of Go a big plus Knowledge of Linux, Windows and other operating systems Good understanding of networking technologies is desired Familiar with Cloud Concepts/Technologies Ability to work in high pace environment Analyse the current products/methods and propose new things Familiarity with Prometheus, Kubernetes, Postgres, Minio, Kibana, Chef, Ansible ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence . THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem - solving skills and are willing to learn and ready to take on problems . Job deliverables: Setup ASIC QA flows for RTL design quality checks. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. Checking the flow errors, design errors & violations and reviewing the reports. Debugging CDC, RDC issues and come up with the RTL fixes. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. Flows or Design porting to different technology libraries. Generating RAMs based on targeted memory compilers and integrating with the RTL. Running functional verification simulations as needed. Job Requirements: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/SystemVerilog Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Preferred experience in AXI4 or NOC protocols or DRAM memory interfaces. TCL, Perl, Python scripting PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . Expertise in Verilog, System Verilog, and Object-Oriented Programming Experience with UVM or similar Verification Methodology Requires strong Computer Architecture knowledge Comfortable in python / perl and editing / maintaining scripts Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Experience with DRAM controllers, DDR Phys or DRAM Interface Protocols is a plus. Strong communication skills and the ability to work independently as well as in a cross-site team environmen ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

SENIOR SOFTWARE SYSTEMS DESIGNER THE ROLE: We are looking for a dynamic, energetic Software Systems Design Engineer to join our growing team. As a key contributor to the success of AMD s products, you will be part of a leading team to drive and improve AMD s abilities to deliver the highest quality, industry-leading technologies to market. The Software Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. PREFERRED EXPERIENCE: Expert in C/C++, Python scripting Good knowledge of Java Virtual Machines just-in-time (JIT) compiler Familiarity with compiler design principles and optimization techniques Knowldge in JVM optimizations and Java bytecode instructions Debug techniques and methodologies . Knowledge of system architecture, technical debug, and validation strategies . Strong understanding of data structures and algorithms Knowlege in assembly language relevant to the target platform for fine-tuning generated code. Prior experience with x86 code generation a plus. Handon experience in profiling and performance monitoring tools to analyze system bottlenecks is a plus Excellent Communication and Presentation skills . ACADEMIC CREDENTIALS: Bachelors or master s degree in Electronics/computer engineering/Electrical . Master s degree preferred. #LI-VV1 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER MTS SILICON DESIGN ENGINEER THE ROLE This is a member of technical staff position for AMD s Central Design Verification Tools & Methodology team. On the tools side, the position has software development and enhancements for custom build tool and infrastructure, which will be used for automated construction, integration, and verification of hardware designs. On the design build flow tool, the position will work with customers to create strong build methodology to improve their efficiency. The AMD Verification Methodology and Tools (VMT) team is a world-wide organization delivering verification methodology, automation around design creation, integration and verification, related software and flows for all AMD project teams and product lines. This position in the VMT team is expected to do tool development, provide guidance on VMT methodology to key AMD programs and new teams. In this capacity he or she will also help collaborate with key internal and external stake holders to drive critical technical decisions across sites. THE PERSON A successful candidate in this position is expected to excel in analytical thinking, problem solving, debugging, tool development and have hands-on experience on resolving critical customer issues. He/she needs to be a self-starter who collaborates well with team members and customers alike to successfully drive tasks to completion. The expectation is to grow into technical expertise with internal tools domain, guide AMD project teams in the same area and drive solutions across the board, world-wide in due course of time. KEY RESPONSIBILITIES The successful candidate will contribute for technical development in the tools and guide others by providing insights in complex design methodologies in this space. The following is a list of key expectations that the candidate should have: Good knowledge of front-end RTL design construction and verification topics, as well as infrastructure Experience in SoC build, infrastructure tools & debugging related issues Good programming aptitude, understanding of C/C++ (any programming language), object-oriented concepts and data structures Good understanding of multi-threaded programming, synchronization objects (and debugging) Knowledge on one versioning system like git/perforce Knowledge of software development processes Expected to learn and adapt to the needs of organization, have team spirit and guide/mentor/train others PRIOR EXPERIENCE Deep experience with EDA software development, ability to architect solutions to deep problems in front end design construction and verification and implementing infrastructure are a must. Key items of interest are: Excellent communication, writing, and presentation skills with experience communicating at executive levels. Managerial and Technical team leadership. Project execution. Customer and partner relations. Leading and guiding the team for success Proposals and strong new initiatives impacting sweeping changes of AMD DV methodology world-wide PREFERRED EXPERIENCE Experience in EDA tool development, scripting and modern software development practices Familiarity with front end design and verification flows in a semiconductor company Strong management experience with DV tools and methodologies team with diverse responsibilities in driving DV methodology and EDA tooling Hands on knowledge and experience with C, C++, Perl, Python, Ruby, Javascript, TCL, and other scripting languages, and UI development Familiarity with infrastructure such as LSF, building complex systems, interfacing with cloud computing, web-based solutions and experience with web-based systems and REST APIs. Familiarity with Linux platform and basic shell commands and environment, Makefiles Experience with Verilog, SystemVerilog, VHDL, DV testbenches is a plus Awareness of the latest developments in the industry on Design Verification topics and software development processes Good to know Knowledge in some of the following topics/technologies -- Event/Messaging Services, databases Good to know Knowledge on Docker / Kubernetes / Containerization , Cloud Services, Microservices and DevOps would be beneficial Strong interpersonal and communication skills and needs to be a team player ACADEMIC CREDENTIALS Bachelors, Masters or PhD degree in Electrical or Computer engineering or Computer Science or Equivalent

MTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As the GSI Partner Development Manager within the Global Commercial Sales organization, you will develop and deliver a cohesive business development strategy to identify and advance new joint Go-To-Market opportunities to drive growth and impact. Your goal will be to increase AMD s GSI market penetration while optimizing investments. You will be responsible to build and maintain relationships with partners to help AMD achieve its business goals, planning and maintaining internal/external operational excellence and improve AMD s market presence. In collaboration with internal and partner teams, you will ensure coordination of business development and process rigor initiatives to elevate perceived customer value. The Person: Does this sound like youWe d love to talk! Experience in a sales and/or management role Knowledge of the companys competitive advantages The ability to think strategically and beyond the status quo Proactive and execution focused leader Action and results-orientation with the ability to make decisions quickly Skilled in developing and sustaining positive interpersonal relationships, with a consistent track record of influencing in a matrixed environment. Creative and innovative in crafting solutions; is results driven with the ability to make decisions quickly. Proven experience in program management, sales strategy and operations, preferably in the semiconductor or technology industry. Demonstrated track record of success in driving sales growth across go-to-market channels, program coordination, C-suite engagement, strategic business planning, and operational excellence. Key Responsibilities: Sales Strategy Development: Develop and refine sales strategies to drive revenue growth within the GSI business. Collaborate with cross-functional teams to align sales strategies with overall business objectives. Lead innovation initiatives to realize broader scale and investment attribution. Collaboration with GSIs: Foster and maintain strong relationships with key stakeholders at GSIs to drive alignment across key solution and vertical priorities. Create and attain joint business plans to achieve business goals, including marketing strategies and partnership models Work closely with the GSI executives and teams to align strategies, elevating customer and executive alignment to maximize mutual success across AMD priorities Maintain operational excellence of pipeline reporting, partnership fund management, and escalation management, through regular cadences weekly, monthly, quarterly business reviews Collaborate with internal and partner teams to plan and execute sales campaigns, workshops, roadshows, events, etc to increase AMD s market awareness to generate opportunities and customer success stories. Ensure GSI partnership adheres to AMD legal framework and requirements. Oversee existing partner programs and manage the process of onboarding new partner programs Recognized voice of customer to influence operations, business unit priorities. Program Management Operational Excellence: Drive programs, lead and optimize operations to ensure efficiency and effectiveness. Implement best practices to streamline processes and build rigor to enhance the overall sales workflow. Data-Driven Decision Making: Leverage data analytics to provide insights and support strategic decision-making. Establish and monitor key performance indicators (KPIs) to evaluate the success of sales strategies (ROI). Market Intelligence: Stay abreast of market trends, be informed on competitor activities, and industry developments. Partner with market intelligence teams to inform sales strategies and identify segmentation and growth opportunities. Preferred Experience: Proven experience in sales strategy and operations, preferably in the semiconductor or technology industry. Experience as a trusted advisor and/or proxy leader, to drive organization needs. Proven track record of success in driving sales growth and operational excellence. Strong leadership skills with the ability to inspire and motivate teams. Demonstrated project and program leadership success Strong analytical and quantitative skills, using data to drive strategic decision-making. Excellent communication, interersonal, facilitation skills. Consistently collaborative style with both internal and external stakeholders. High level of proficiency in MS office (Word, Excel, PowerPoint), and in data analysis and presentation.

The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. PREFERRED EXPERIENCE: Years of experience 9+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge. Exposure to UPF based low power RTL verification Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As the SoC Subsystem Physical Design Lead, you will lead the physical design and implementation of critical subsystems within advanced SOC designs. Your role will involve driving the physical design flow from floor planning through final sign-off, collaborating closely with cross-functional teams to meet stringent power, performance, and area (PPA) targets. THE PERSON: This position requires deep technical expertise in physical design methodologies and tools, as we'll as the ability to lead and mentor a team of physical design engineers. KEY RESPONSIBILITIES: Own the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization to meet PPA goals. Work closely with RTL, DFT and IP teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance. Collaborate with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top level Lead clock tree synthesis, manage clock skew, insertion delay, and ensure timing closure across all corners and modes. Address timing violations and signal integrity issues. Implement power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance. Develop and optimize custom scripts in Tcl, Perl, or Python to streamline physical design tasks and improve workflow efficiency. Mentor and guide junior physical design engineers, sharing best practices and providing technical guidance to improve team efficiency and expertise. PREFERRED EXPERIENCE: Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power optimization techniques, Upf, including clock gating and multi-voltage domain design Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, Redhawk-SC Scripting skills in Tcl, Python, or Perl to enhance automation and streamline physical design tasks. Familiarity with DRC, LVS, and other physical verification processes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. KEY RESPONSIBILITIES: 1. Bring deep knowledge and experience in Physical design and apply them to large, challenging, leading-edge designs to ensure high quality on time delivery. 2. Bring significant experience in effective team management to help mentor, coach and grow the Server SOC Physical Design Team with an emphasis on positive influence on team morale and culture 3. Technically manage different aspects of Physical Design including Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off. 4. Experience and understanding of flow development and scripting. 5. Strong Technical problem and debugging solving. PREFERRED EXPERIENCE: 1. 15+ years experience in ASIC Design with relevant Physical Design Skills 2. Minimum BSEE/CE, or equivalent degree, Masters is preferred. 3. Must have prior experience leading Physical Design teams of at least 10 members 4. Excellent analytical and problem-solving skills along with attention to details. 5. Strong written and verbal communication, Time Management and Presentation Skills. 6. Must be a self-starter, and able to drive independently and efficiently challenging and time critical tasks to on-time completion. 7. Forward looking and dependable leader who proactively identifies and resolves issues and roadblocks before they become bottlenecks or showstopper. 8. Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, mut have strong technical management skills and provide a positive influence on team morale and culture 9. Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics required. ACADEMIC CREDENTIALS: Bachelor s or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.

We are looking for an adaptive, self-motivated design for test verification engineer to join our growing server SOC DFT team. Identified candidate will be responsible for high quality verification of our DFT features for next generation server SOCs. This team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion design for test, and verification. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Create and execute test plans for DFT features for next generation EPYC server SOCs. Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level. Will be creating test bench and verification infra using SV or C++. Debug regression test failures and root cause design issues, identify verification gaps and address the same. Debug fails and root cause them to design / verification issues. Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc. Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc. Work on code and functional coverage. Generate patterns for post silicon testing and support ATE bring up. Carryout post silicon debugs and help post silicon team achieve high coverage. Work on emulation platforms to augment verification. PREFERRED EXPERIENCE: Prior experience in verifying DFT features at subsystem / SOC level. Proficient in standard simulation debug tools such as VCS, Verdi etc. Experienced with Verilog, C, C++, Linux and Windows environments. Scripting language experience: Perl, Python,Ruby, Makefile, shell preferred. Knowledge in few of the DFT features such as JTAG, Memory BIST, Logic BIST, Scan, ATPG is highly desirable Exposure to post silicon debugs and bring up highly is desired. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics/Electrical Engineering.

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering