We are looking for an MTS (Member of Technical Staff) Engineer to join our Open Source Graphics team and contribute to the amdgpu kernel-mode GPU driver for future AMD Radeon and Instinct products. Join our team developing open-source GPU drivers for Linux. As leading contributors to Radeon Mesa graphics and multimedia drivers in major Linux distributions, our software powers cutting-edge automotive and gaming products. We deliver the GPU Linux software stack for discrete GPUs and APUs, work on pre-silicon development, develop new features, and create essential software components for graphics and compute. THE PERSON: The best candidates will have excellent C programming skills and a demonstrable understanding of graphics systems software, along with comprehensive knowledge of computer architecture and operating systems fundamentals. In this position, you will have the opportunity to work on the latest innovative AMD platforms. We have a passion for creativity and pushing technology to its limit, which will be fully tested and applied in this role. You will work closely with experts from GPU and adjacent domains in system software and hardware across AMD to build the best products in the segment. KEY RESPONSIBILITIES: Contribute enhancements to the amdgpu kernel-mode GPU driver for AMD graphics products . GPU driver bring-up and qualification on new hardware platforms. GPU driver performance analysis and optimization. Investigation, analysis, and resolution of issues as reported by Customers and QA. Collaborate closely with developers in the open source graphics development community . PREFERRED EXPERIENCE: 7+ years of experience developing system software and kernel mode drivers for Linux and derivatives . Demonstrable proficiency in C programming, developing multi-threaded kernel mode drivers. Excellent understanding of computer architecture, operating systems concepts, memory management, and concurrency. Strong communication and interpersonal skills. Ways to stand out from the crowd: Experience working in the Linux DRM/KGD (Direct Rendering Manager / Kernel Graphics Driver) subsystem . Conceptual understanding of user-space compositors, eg Wayland and X.org compositors, Android HWC, or QNX Screen. Track record of open source contributions . ACADEMIC CREDENTIALS: Bachelors or M asters degree (preferred) in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: required to be experienced in power estimation, analysis, optimization experience with tools PTPX/Power Artist physical design experience with ICC/Innovus, and saif based power optimization is a plus front end design knowledge data paths understanding, reviewing waveforms etc,. is a plus knowledge of power management methodologies (including clock gating, power gating, voltage frequency scaling, etc..) is a plus Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Integrate tests for DPPM calculation in at-scale data center automation environments. Support DPPM test content execution, which includes occasional weekend monitoring and triage work. Technically lead the local team and work with cross-functional teams to proactively improve DPPM test content efficiency. Do first level debug of DPPM execution failures and apply corrective actions of submit tickets for second level debug support. Collaborate with cross-functional team in developing SW tools to improve SoC Validation coverage Debug timeline Drive solid solutions to execution issues. PREFERRED EXPERIENCE Technical leadership experience in a system/platform post silicon environment. Hands-on experience with System Validation Automation Tools and Infrastructure such as Ansible, PyInfra, Java/Shell Scripting, Python, Ruby, Perl, GIT, Jenkins Extensive hands-on experience with design and implementation of various test methodologies, test automation, continuous integration systems, and server deployment methodologies. Ability to structure and execute complex analysis, draw insights, and communicate summary findings/recommendations to senior management. Ability to network, build relationships and drive effective decision-making across multiple functions and levels within the organization Highly organized, able to prioritize, and juggle multiple work streams to tight deadlines Good knowledge of modern OS kernel (MS, Linux) and programming / scripting language (C/C++, Python, Perl, ) Prior experience with server systems, platform level debug. Prior experience with Linux server administration and Linux boot flow. Experience with Computer Architecture concepts and silicon features Reliability, Availability and Serviceability (RAS) x86 is a plus

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Drive technical innovation to improve AMD s capabilities across product development and validation, including software tools and script development, technical and procedural methodology enhancement, and various internal and cross-functional initiatives . C onvert feature specifications into test cases (manual and automated) that will cover several types of testing - boundary, negative, functional, etc. W ork with multiple teams and tracking test execution to make sure all features are validated and optimized on time . W ork closely with supporting technical teams to validate new software features and new OS (Operating System) introduction . Le ad collaborative approaches with multiple teams . M entor others to achieve integrated projects . PREFERRED EXPERIENCE: Excellent Programming skills in C++ (STL, C++11, C++14, C++17 etc ) Operating system (Windows & Linux) Linux Internals, system programming (IPC, posix threads, system calls) Experience with eBPF, perf Multi-threading Database - MySQL Experience in developing profiling tools is a plus. Debug techniques and methodologies . Good knowledge and hands on experience in PC (Personal Computer) configurations (both Software and Hardware) with methods of Troubleshooting . ACADEMIC CREDENTIALS: Bachelors or master s degree in electrical or computer engineering . Master s degree preferred.

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Manage complex employee relations related investigations with limited supervision, honoring complete confidentiality, neutrality, complete fairness, unbiasedness and exercising best workplace investigation practices. Should be able to independently handle allegations of discrimination, harassment, retaliation, bullying, misconduct, bias, and other inappropriate behavior across regions like India, Southeast Asia locations. Conduct robust investigations into employee complaints and allegations of misconduct in a timely, fair, and balanced way. Identify and assess the scale and scope of alleged or confirmed conduct that is deemed inappropriate, impermissible, or unacceptable. Partner with legal counsel as needed. Follow thorough investigations through resolution. Maintain accurate files, documentation, and follow-up. Effectively handle employee relations issues and concerns, minimizing corporate risk and improving employee experience. Must exhibit strong professional judgment, emotional intelligence, and collaborative across functions and regions, should communicate effectively with cross-functional partners in HR, Legal, HR Ops, TA, TR, Govt Relations and the business. Must be able to articulate India local laws and other provide guidance to the leadership team for any Labor compliance and law regulation changes. India SPOC to Leadership on advice, consult for any difficult employee conversations, support in any ER conflict resolution. Partner and assist the Corporate Investigations team for conducting local employee investigations. Work collaboratively on employee relations matters such as corrective actions including warnings or performance improvement plans. Assess policy issues regarding legal risk; work with legal advisors to ensure compliance to and understanding legislation. Proactively lead the delivery and deployment of new ER Practices and review/redefine existing ones. Support all Labor compliance activities/audits and state laws. Ensure continuous improvement by actively identifying gaps, proposing, and implementing changes and innovative solutions. Develop metrics and leverage on analytics to track progress of ER programs and create comprehensive review decks for Leadership team. Build and maintain online repository of knowledge updates best practices for easy access and retrieval. Improving employee experience in all HR life cycle functions Participates in the development and delivery of management training programs designed to advance the employee relations skills of people managers. Facilitate training to build employee relations skills among people managers. Assist with ad-hoc employee relations and HR department projects. Make suggestions to leaders and HR Business Partners on employee engagement, policy or process improvements based on trends and risks. PREFERRED EXPERIENCE: Strong ER experience gained through increasingly responsible positions within Human Resources with a particular focus on employee relations, HRBP. Experience in a high growth, fast paced matrix environment. Strong problem-solving skills and ability to determine the root cause of issues. Highly collaborative and able to work both within and across teams globally. Ability to work through ambiguity, think creatively, be flexible and roll-up your sleeves. Exceptional communication skills, case documentation and report writing skills, executive leadership presentation and relationship development skills. Professional, confident manner and poised and articulate demeanor. Ability to work effectively with a wide array of personality types and all job levels. Demonstrated history of exemplary ethics and integrity, including ability to handle and maintain confidential information. Active commitment to the identification and appropriate resolution of all business issues, whether they are rooted in business problems or are pure compliance concerns. Demonstrated ability to assume sole and independent responsibility for projects. Ability to exercise discretion related to sensitive employee matters.

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Synthesis of Complex IPs, constraint developement. Physical aware activty Floorplan,Placement,clock tree synthesis routing. Develop feedback to RTL team for physically driven microarchirtecture changes, Manage data for shared design across multiple projects. corrdintation with multiple SOC for complex IPs Lead team for junior team member,guide them and help techincal areas. PREFERRED EXPERIENCE: Understanding of Physical design and synthesis design cycle. 8+ experience in physical design and syntheis domain ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering/Electronics Engineering

As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have 10 to 15yrs of work experienc e. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis . Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer/Electronics/Electrical Engineering

The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Experience in RAL is preferred ACADEMIC CREDENTIALS: Bachelor s or master s degree in Electronics or Electrical or Computer engineering

Architect, analyze and optimize high-performance GPU-centric SoCs for Cloud Computing, and Machine Learning acceleration. Develop performance models and methodologies. Propose solutions to enhance performance and optimize power for next-generation data center systems. The Person: As a system performance architect on our design engineering team, you will help propose and implement solutions to our next generation GPU SoCs and optimize data center system application performance. Key Responsibilities: Participate in microarchitecture exploration, performance modeling, and analysis for next-generation GPU systems. Understand the design and architecture, propose solutions to enhance performance. Help with micro-benchmarking, workload characterization, competitive analysis, bottleneck identification, and optimization. Develop tools and methodologies for performance analysis of workloads. Communicate, propose, and implement solutions to enhance processor and system performance. Preferred Experience: Strong knowledge of GPU, CPU, SoC or computer system microarchitecture Experience with the development and usage of computer system performance models Some experience with computer workload analysis Strong programming skills, including experience with C++ and Python (or similar) Academic Credentials: Ph.D. in Computer Science / Electronics Engineering, and 3+ years of experience as a Performance Engineer M.S./M.Tech. in Computer Science / Electronics Engineering, and 5+ years of experience as a Performance Engineer B.Tech. in Computer Science / Electronics Engineering, and 7+ years of experience as a Performance Engineer

Architect, analyze and optimize high-performance GPU-centric SoCs for Cloud Computing, and Machine Learning acceleration. Develop performance models and methodologies. Propose solutions to enhance performance and optimize power for next-generation data center systems. The Person: As a system performance architect on our design engineering team, you will help propose and implement solutions to our next generation GPU SoCs and optimize data center system application performance. Key Responsibilities: Participate in microarchitecture exploration, performance modeling, and analysis for next-generation GPU systems. Understand the design and architecture, propose solutions to enhance performance. Help with micro-benchmarking, workload characterization, competitive analysis, bottleneck identification, and optimization. Develop tools and methodologies for performance analysis of workloads. Communicate, propose, and implement solutions to enhance processor and system performance. Preferred Experience: Strong knowledge of GPU, CPU, SoC or computer system microarchitecture Experience with the development and usage of computer system performance models Some experience with computer workload analysis Strong programming skills, including experience with C++ and Python (or similar) Academic Credentials: Ph.D. in Computer Science / Electronics Engineering, and 3+ years of experience as a Performance Engineer M.S./M.Tech. in Computer Science / Electronics Engineering, and 5+ years of experience as a Performance Engineer B.Tech. in Computer Science / Electronics Engineering, and 7+ years of experience as a Performance Engineer

Ideal candidate should have 12+ years of experience in technical roles involving tool development with some focus in areas of regression management like scheduling, executing harness, failure analysis & assignment and reporting. Also should have hands-on experience in working with DevOps env tools including cloud, databases & AI/ML technologies. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Drive and improve implementation of test infrastructure to provide robust test environment to developers & testers Analyze, optimize & improve current architecture of various components of test Infra tools including integration Implement containerized test infra with full on-prem/cloud portability Compatible with various job management systems like LSF, SLURM, and Kubernetes orchestration framework Drive & Implement strategies to leverage AI/ML models at various stages of testinfra Drive & Implement Next Gen QOR (Quality of results for FPGA designs) regression execution & reporting Overseeing and providing development support to team members. Collaborating with cross-functional teams, providing technical support, and troubleshooting migration to next generation tools, CI/CD, containerization, Kubernetes, and cloud tooling issues. Creating comprehensive documentation, mentoring junior team members, and conducting training sessions PREFERRED EXPERIENCE: Professional 12+yrs of technical experience and at least 5 years experience in design & implementation of product developments Experience in developing tools around test Infra automation Expert in structured & OOP in Python Proficiency in Scripting and automation languages (eg, Python, Bash, Csh,..) Linux & Windows shells working environment Understanding of AI/ML principles and some experience in applying LLM & ML models in tool development Experience with working in DevOps environment like GitHub, Perforce version control systems, containerization technologies like Docker, Kubernetes orchestration and CI/CD pipelines using Jenkins or Github actions Additionally, experience with monitoring and logging tools for containerized environments (eg, Prometheus, Grafana, ELK Stack) Excellent problem-solving abilities with a keen eye for detail are highly valued ACADEMIC CREDENTIALS: bachelors or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

The ideal candidate will participate in all aspects of the software development life cycle; he or she will be expected to provide full ownership of specific components and drive assignments to completion: Design and implement Bootloader/ Trused OS/ Firmware supporting security features in Trusted Execution Environment Create novel tools and methodologies to optimally validate hardware and software functionality Engage in pre-silicon development activities including emulation/ simulation Engage as a teammate, talking to multi-functional development teams Assist in resolution of customer, quality and certification issues Actively participate in design reviews and discussions Debug/fix existing issues and r esearch alternative, more efficient ways to accomplish the same work PREFERRED EXPERIENCE: Experience developing Linux Device Drivers/ Bootloader / ROM code Experience in applied Cryptography, Security protocols, Secure boot will be an added advantage Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with software development processes and tools such as debuggers, source code control systems (GitHub) is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Develop and optimize voltage scaling and isolation strategies across multiple power domains. Work with the physical design and RTL teams to ensure voltage islands and isolation cells meet design specifications. Create and maintain Unified Power Format (UPF) files to define power intent across the design. Ensure proper definition of power domains, retention, and power shutoff requirements to meet power integrity. Collaborate with the verification team to implement power-aware verification strategies using UPF, ensuring all power-related checks are met. Perform power analysis to identify potential issues and optimize the design. Work closely with the architecture, RTL, DFT, and physical design teams to integrate power management requirements, ensure alignment on power specifications, and resolve power-related issues. Document power management strategies, UPF implementation details, and analysis findings. Present findings and recommendations to design and management teams. Provide guidance and training to junior engineers and cross-functional teams on DFP, VSI, and UPF best practices and methodologies. PREFERRED EXPERIENCE: Expertise in UPF power intent formats and power-aware verification flows. Strong knowledge of DFP techniques, including power gating, multi-voltage, clock gating, and DVFS. Experience with VSI, power domain partitioning, and isolation cell management. Strong problem-solving, analytical, and communication skills. Ability to collaborate effectively across multiple teams and manage complex design requirements. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering.

The focus of this role will involve driving the physical design flow from floor planning through final sign-off, collaborating closely with cross-functional teams to meet stringent power, performance, and area (PPA) targets. THE PERSON: As the SoC Subsystem Physical Design Lead, you will lead the physical design and implementation of critical subsystems within advanced SOC designs.. This position requires deep technical expertise in physical design methodologies and tools, as we'll as the ability to lead and mentor a team of physical design engineers. KEY RESPONSIBILITIES: Own the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization to meet PPA goals. Work closely with RTL, DFT and IP teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance. Collaborate with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top level Lead clock tree synthesis, manage clock skew, insertion delay, and ensure timing closure across all corners and modes. Address timing violations and signal integrity issues. Implement power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance. Develop and optimize custom scripts in Tcl, Perl, or Python to streamline physical design tasks and improve workflow efficiency. Mentor and guide junior physical design engineers, sharing best practices and providing technical guidance to improve team efficiency and expertise. PREFERRED EXPERIENCE: Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power optimization techniques, Upf, including clock gating and multi-voltage domain design Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, Redhawk-SC Scripting skills in Tcl, Python, or Perl to enhance automation and streamline physical design tasks. Familiarity with DRC, LVS, and other physical verification processes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Will be working as a member of a cross geographic pre_silicon verification team to verify a next generation AI engine. Will be working with design, architecture team to verify micro-architecture and design across multiple platforms. Responsible for a comprehensive verification plan and drive the implementation of verification test cases from applications and other sources. Responsible for regression, verification infrastructure development Mentoring junior engineers PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools. Proficient in using UVM testbenches and working in Linux and Windows environments. Experience in specifying and developing the verification infrastructure for verifying CPU/DSP/Vector-Datapath designs. 4+ years of experience in the verification with experience of CPU/Video/DSP/vector processors, SIMD is a plus. Strong foundation in SoC architecture and verification of multi-core processors including SIMD, Vector processors, floating point, etc is a plus. Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc Strong experience in HDL, verification, and general computational logic design/verification concepts Developing UVM based verification frameworks and testbenches, processes and flows. Strong analytical problem solving, and attention to detail. Excellent written and verbal communication skills. Excellent interpersonal skills, self-motivated ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Engineers with at least 3 years of experience with BIOS, firmware, or system software development Good knowledge about ACPI, USB, PCIE, SATA and other PC industry standard Good at X86 assembly and C language Familiar with at least one BIOS code base (AMI, Insyde or UDK open source) UEFI experience is required Experience in BSP development/Boot loader (uBoot)/CoreBoot is a plus Experience in BIOS related tools development is a plus Experience in Video BIOS development is a plus. ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

We are seeking an engineer to join our team that will thrive in a fast-paced work environment, using effective communication , problem-solving and prioritization skills. Individuals that are well organized, show great attention to detail, and employ critical thinking are well-suited for our team. THE PERSON : Th is AMD (Advanced Micro Devices) team is looking for a senior level person that can help guide the team, mentor up coming developers, provide long range strategy, and is willing to jump in to help resolve issues quickly. You will be involved in all areas that impact the team including performance , automation, and dev elo p ment . The right candidate will be informed on the latest trends and become prepared to give consultative direction to senior management. KEY RESPONSIBILITIES: A powerful desire to learn new skills and understand new features as they are added Proven record of accomplishment of working within and across groups . Effective communication skills Responsible for exploring opportunities to improve product Work closely with other team members to understand design architecture and to propose solutions to improve and enhance product s PREFERRED EXPERIENCE: Exposure to systems architecture Experience running, analyzing, and system benchmarks Solid programming skills in Python, C, or C++ ACADEMIC CREDENTIALS: Bachelor s or Master s in Electrical Engineer, Computer Engineering, Computer Science, or a closely related field

Guiding the team on PNR for Block closure Physical Implemenation of Block Working on PPA improvemnets Cleaning up the DRC and LVS signoff the block in Timing, IR and PV P REFERRED EXPERIENCE : 14+ years of experince in Physical design Excellent skills in PNR using Fusion Compiler tool Hands on expereince working on latest nodes 6 NM and below Expert in scripting TCL/Perl/ Python Good understnding of Pkg and full chip floorpan ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics Engineering/computer engineering/Electrical Engineering