1. Must have SoC implementation knowledge with deep level expertise in at least one domain. 2. Have responsibility for processes of significant technical importance and for results in SoC implementation and/OR related areas. 3. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation. 4. Influences technical decisions that have a significant impact on final product. 5. Requires limited supervision and is evaluated according to project performance. 6. Coaches and mentors less experienced staff; influences others as a technical leader. 7. very good communication and presentation skills 8. Proficiency in scripting Required Skills: 1. SoC implementation expertise. Multi million gates integration. 2. Low power implementation, Constraints validation, Formal verification 3. Floorplanning, Power planning. 4. Clock Tree Synthesis (CTS). 5. Awareness of Synthesis, SCAN and DFT implementation 6. Static Timing analysis (STA). 7. Analysis: IR, EM, Noise. 8. Physical Verification. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics engineering/Electrical Engineering

As a Full-Chip Floor Planning Engineer, you will play a crucial role in the physical design and implementation of advanced semiconductor chips. Working closely with RTL designers, physical design teams, and other cross-functional groups, you will be responsible for full-chip floor planning, enabling efficient design layouts, and optimizing the placement of major functional blocks. This position requires a solid understanding of physical design and chip architecture, as well as experience in floor planning tools and methodologies for high-performance and low-power design. Technical Requirements Proven experience in top level floor planning/block partition which includes physical partition, pin/feedthrough placements and repeaters assignments. Experience in SOC floorplan aspects like FullChip clock spine distribution, analog integration, push down macros, GPIOs. Proficiency in EDA tools such as Cadence, Synopsys ICC, Calibre, etc Strong scripting skills in Tcl, Perl, or Python for automation In-depth knowledge of upf, floor planning concepts, including chip partitioning, placement, and routing methodologies. Experience with power, timing, and area optimization techniques Familiarity with design rule check (DRC) requirements. Responsibilities Lead the floor planning process from RTL to GDSII, optimizing block placement, chip partitioning, and routing feasibility to ensure timing, power, and area constraints are met. Collaborate with RTL, block-level, and physical design teams to integrate IPs, macros, and other design components efficiently at the top level Work on area and power optimization techniques to achieve a highly efficient chip layout. Perform what-if analyses to evaluate trade-offs and optimize design parameters. Interface with architecture, package, and timing teams to align on chip-level requirements and ensure the physical design meets performance and design intent. Identify potential design issues early in the floor planning process and collaborate with stakeholders to develop and implement mitigation strategies Develop, enhance, and maintain custom scripts to automate repetitive tasks within the floor planning flow, ensuring efficiency and accuracy.

Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL). Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe , PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing. Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies. Experience: 8+ years of experience in SerDes verification or high-speed communication verification. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools. Knowledge of high-speed serial protocols such as UCIe , PCIe, Ethernet, USB, DDR, or custom protocols. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams. Skills: Solid understanding of SerDes architectures, link training, and equalization. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance). Familiarity with hardware description languages (HDL) like VHDL or Verilog. Strong analytical, problem-solving, and communication skills. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication. Preferred Skills: Experience with Python, Perl, or similar scripting languages for automation. Exposure to high-speed memory interface design and verification, including DDR controller IP verification. Functional coverage, assertions knowledge in SV/UVM. Ability to work in a fast-paced environment and manage multiple verification tasks. Strong team player with good interpersonal and communication skills.

The software Technical Marketing team is looking for someone to drive features, methodology and collateral around the software development flow for machine learning applications. THE PERSON: We are looking for a highly motivated and skilled Machine Learning and AI Technical Marketing Engineer with experience in system design, as well as FPGA and Embedded software Tools, to scale the teams ability to deliver customer focused solutions for current and next generation AECG Platforms. Candidates should have a desire to deliver solution that enable customers to accomplish their goals, be self-motivated, possess the ability to work well within a distributed team environment and have the ability to easily communicate technical concepts in simple terms. Key Responsibilities: Collaborate with market segment architects and business leads to create customer focused machine learning and signal processing applications collateral to address the complex needs of customers in Aerospace and Defense, Automotive, Wired and Wireless Networks, Test and Measurement, Medical, Industrial and Vision markets, and Audio Video Broadcasting. Work closely with Vivado, Vitis and Vitis AI Tools, IP, system software, and boards marketing and marketing teams to support customers and drive deliverables as part of the overall solution plan for existing and next generation embedded silicon devices. Interface with product marketing and engineering teams to prioritize and align solution deliverables during release planning processes. Support customers using the Vitis AI and other tools for Machine Learning applications. Present solution progress updates to executive and deliver solution, silicon, and customer application presentations to internal marketing and engineering teams. Drive solution deliverables to support machine learning applications in FPGA and SOC product families. Preferred Experience: Tenured industry experience with Machine Learning programming, optimization and debug techniques. Proficient industry experience with Embedded software programming, optimization and debug techniques. Ability to understand a broad set of applications from traditional FPGA centric applications such as Wired and Wireless Communications, Aerospace and Defense and general Digital Signal Processing and to emerging applications in Artificial Intelligence, Machine learning, Vision Processing and Autonomous Driving. Have experience with FPGA and Adaptive SoC products and exposure to Vivado, Vitis and Vitis AI design tools. Have experience with system level analysis, such as interface and memory bandwidth, as well as compute and dataflow analysis. Have experience with some or all of the following ML networks for embedded applications: CNNs, RNNs, MPLs, GNNs and Transformer Ability to break down large complex problems into manageable deliverables and be able to manage and prioritize requirements from many stakeholders. Thrive in a fast-paced environment at the forefront of new technology and invention. Beneficial to have Project Management experience, excellent organizational skills, and a process-oriented mindset. Exp : B.Tech / M.Tech with 15+Yrs of exp

Architect, Design and Develop Storage solutions on DPUs in the areas of NVMe-PCIe NVMeoF(TCP, RDMA), VirtIO. Build Innovative solutions and solve challenging problems in areas of Storage Disaggregation, Virtualization, Storage services (Encryption, Compression, Replication and Erasure Coding), etc Contributions to Patents, Standards and Open Source Initiatives Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring ups Debug/fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Prior Storage experience in any of NVMe, NVMe-oF, VirtIO, SCSI/FCP, iSCSI, RDMA and TCP areas Strong object-oriented programming background, C/C++ Strong systems programming background Exposure to Linux block layer, block device drivers (linux, ESXi, Windows), QUEM/KVM Virtualization, PCIe, TCP and basic networking is added advantage Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Motivating leader with good interpersonal skills ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Work with internal and external customers to help debug problems running their workloads on the models. Collaborate with cross-functional teams to find quality solution for all issues. Develop test plans and tests functionality of the models. Develop high-performance functional models for AMD SoCs and platform. Improve functionality, stability, and performance of existing models. Develop new, innovative debug features. PREFERRED EXPERIENCE: Experience writing high-performance system and application software in C/C++ for Windows and/or Linux environments Good understanding of system architecture and system software development is desirable Exposure in functional modeling and architecture simulation is desirable ACADEMIC CREDENTIALS: Bachelor s or Master s in Electrical Engineer, Computer Engineering, Computer Science, or a closely related field

Work with internal and external customers to help debug problems running their workloads on the models. Collaborate with cross-functional teams to find quality solution for all issues. Develop test plans and tests functionality of the models. Develop high-performance functional models for AMD SoCs and platform. Improve functionality, stability, and performance of existing models. Develop new, innovative debug features. Work closely with architecture teams to understand and model new designs. PREFERRED EXPERIENCE: Experience writing high-performance system and application software in C/C++ for Windows and/or Linux environments Good understanding of system architecture and system software development is desirable Exposure in functional modeling and architecture simulation is desirable ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer or Electrical Engineering or equivalent

Design and develop efficient solutions targeting AMD emulation and prototyping efficiency Work with EDA vendors to implement best practices to ensure most optimal flows Develop solutions to ensure emulator workload execution performance tracking for the leading-edge performance/throughput. Evaluate, implement and help to improve FPGA-based technologies and platforms Analyze and improve multitude of data, collected through emulation Contribute to testbench development and improvement Be true part of the great team, priding itself in collaborative, supportive and open culture PREFERRED EXPERIENCE: Background in emulation or prototyping, familiarity with flows and infrastructure Development skills in Python/Perl, C/C++, Verilog, Unix shell, System Verilog, UVM Proficiency in Unix environment, administrative level preferred Familiarity with SQL is a plus Other useful skills: Perforce, GIT, Jenkins, ELK, PowerBI, VHDL ACADEMIC CREDENTIALS: Bachelor s or Master s in Electrical Engineer, Computer Engineering, Computer Science, or a closely related field

We are looking for a dynamic, energetic Lead / Principal Systems Design Engineer to join our growing team. As a key contributor to the success of AMD s product, you will be part of a leading team to drive and improve AMD s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: As a Leader in Systems Design Engineer ing , you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards p roduct development, definition, and root cause resolution. KEY RESPONSIBILITIES: Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across all AMD embedded products. Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup) Test interactions between various SoC features using validation infrastructure. Lead debug and drive root-cause analysis for SoC related issues Collaborate with cross-functional teams in developing tools to improve SoC validation and debug. Work with cross-functional teams to improve post-silicon validation test strategy, methodology, and process. Manage and track technical issues, risks and priorities. Manage executive communications, including program status, risks and opportunities. Driving technical innovation to improve AMD s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives. PREFERRED EXPERIENCE: 12+ years of relevant experience Programming/scripting skills (eg C/C++, Perl, Ruby, Python) Debug techniques and methodologies Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion ACADEMIC CREDENTIALS: Bachelors or M asters degree in electrical or computer engineering

We are looking for an adaptive, self-motivative Synthesis/PD/STA engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects for the new features to be implemented in layout End-to-end RTL to GDS implementation of complex IPs and supporting the SOC customers Working with RTL team to resolve timing and congestion issues Build and develop methodology to converge multiple PNR blocks from RTL to GDS Analyze design metrics and make implementation choices to optimize PPA PREFERRED EXPERIENCE: ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Expertise in synthesis and physical design flows Modern SOC tools including Synopsys Fusion compiler, Primetime and Redhawk TCL, Perl, Python scripting Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Mimimum 3 years of industry experience ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Physical Design Closure of critical partitions in complex IPs PREFERRED EXPERIENCE: 4-6 years of expereince in Physical Design Should have done partition closure in at least 3-4 tapeouts Should have exposure to one of signoff verification flows ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering / Electronics Engineering

Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partne rs PREFERRED EXPERIENCE: Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Windows, Linux and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Experience in performance tuning and debugging system level issues Experience in DPU or AI-NIC development is a huge plus ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Develop high-quality platform validation software tools using C++. Write clean, maintainable, and efficient code. Collaborate with cross-functional teams to define, design, and add new features. Debug and maintain existing codebase to ensure software stability and performance. Participate in code reviews and provide constructive feedback to peers. Troubleshoot and resolve software issues as they arise PREFERRED EXPERIENCE: Extensive experience with C++ programming and basic knowledge on scripting languages like Python and shell script. Experience with QT, STL, Boost and any front end back end development in C++, ReactJS / AngularJS is plus. Software applications design and development experience. Ability to do RD and come up with design proposals. Experience in the Semi-conductor domain with CPU or GPU SW development experience. Should have good understanding of x86/ARM architecture. Experience in Memory, PCIe and USB domain would be good. Should have good analytical and debug skills. Ability to adapt to new technologies and learn quickly Good understanding of operating system internals is preferred (windows / Linux). Familiarity with Git version control system. Excellent communication skills to be able to not only work as part of the team but also interact and engage with other engineers at remote design centers. Various necessary soft skills such as ability to work with minimal input directions, teamwork, initiative and positive attitude. ACADEMIC CREDENTIALS: Bachelors or master s degree in electronics or computer engineering .

AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate an expert team. You will manage a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies. THE PERSON: The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. KEY RESPONSIBILITIES: ASIC design verification experience 12+ years Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor. Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor ISA. Experience with Cache, Coherency and Data-Consistency verification. Experience in clocking, reset, power-up sequences and power management verification. Understanding of low power design verification techniques is a plus. Lead verification team from all aspects of the deliverables. Mentor the junior members of the verification team to meet the team goals Represents AMD to the outside technical community, partners and vendors Collaborate with SOC team, multi-geographical design teams for alignment of features / scoping / problem-solving. Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, and good organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design/RTL and physical design flow is highly desired. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Design and develop Linux kernel device drivers, with a strong emphasis on networking drivers and RDMA technologies. Continuously review and optimize kernel driver code for RDMA performance improvements. Perform rigorous testing and validation of driver software, including developing simulation models to ensure accuracy and reliability. Collaborate with cross-functional teams to integrate and optimize RDMA transactions within the networking stack. Participate in code reviews to ensure code quality and adherence to best practices. QUALIFICATIONS: Bachelors or Masters degree in Computer Science or a related field. 10+ years of experience as a Software Developer with 3-4 years of experience in programming. In-depth knowledge of Linux kernel development and device drivers. Proven experience in developing networking drivers. Desirable experience with RDMA technologies and transactions. Ability to create detailed documentation for driver designs and procedures. Exceptional problem-solving and debugging skills, especially in the context of kernel drivers. Strong communication skills and the ability to work effectively within multidisciplinary teams. GREAT TO HAVES: Familiarity with networking protocols and technologies beyond RDMA. Experience in tuning and optimizing networking performance. Proficiency in Linux kernel modules. Previous contributions to open-source projects related to Linux kernel development. Working experience with programmable ASICs and/or p4 language

Develop high-quality platform validation software tools using C++. Write clean, maintainable, and efficient code. Collaborate with cross-functional teams to define, design, and add new features. Debug and maintain existing codebase to ensure software stability and performance. Participate in code reviews and provide constructive feedback to peers. Troubleshoot and resolve software issues as they arise PREFERRED EXPERIENCE: Extensive experience with C++ programming and basic knowledge on scripting languages like Python and shell script. Experience with STL, Boost and any front end & back end development in C++, ReactJS / AngularJS is plus. Expertise in development and maintenance of Multithreaded/Concurrent applications for windows and Linux OS. Experience working with IPC mechanisms and Synchronization techniques. Familiarity with CMake, Makefiles and build systems for cross-platform development. Should have good analytical and debug skills. Ability to adapt to new technologies and learn quickly Good understanding of operating system internals is preferred (windows / Linux). Familiarity with Git version control system. Excellent communication skills to be able to not only work as part of the team but also interact and engage with other engineers at remote design centers. Various necessary soft skills such as ability to work with minimal input & directions, teamwork, initiative and positive attitude. ACADEMIC CREDENTIALS: B achelors or Masters degree in Electrical Engineering, Mathematics, Computer Science, Engineering, or an equivalent

Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partne rs PREFERRED EXPERIENCE: 10 years of experience in software development in domains of networking, RDMA, or system software Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience working in different operating systems or server environments is a plus Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Experience in performance tuning and debugging system level issues Experience in DPU or AI-NIC development is a huge plus ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

AMD is seeking a Platform Emulation Engineer to join our Data Center GPU organization Our products support the rapidly scaling Data Center and High-Performance Compute infrastructure You will be an integral member of the Platform emulation team responsible for emulation infrastructure development, execution and debug of critical firmware used in our HPC and ML products, developing test plans and execute test cases to enhance silicon test coverage, train and support validation teams on emulation technology, build and execute industry standard HPC benchmarks and applications on the emulator As a platform emulation engineer you will have an opportunity to work on bleeding edge SoC architecture and technology and participate in development of emulation infrastructure to enable pre-silicon activities to ensure high quality Silicon and fast time to market You will work alongside our team of innovative engineers to support the deployment of AMD s Instinct ML products targeting Supercomputers and Data Center workloads KEY RESPONSIBILITIES CPU/GPU Firmware/OS bring up and debug using leading edge emulators (Veloce, Zebu, Palladium) Develop/modify/enhance functional/stress tests to find silicon bugs on emulator Validate features in firmware including but not limited to RAS, Resets, Power management, Secure boot, Virtualization Validate multi-socket configurations in emulation using firmware Bring up the full AMD graphics software stack in emulation Bring up ML/AI applications in emulation Collaborate with workloads and SW teams, run apps in multi-socket configurations, collect and interpret results for debug and tuning Checkout of IP features in software simulation model as a pre-step for emulation Interface with Central Emulation team responsible for helping to develop, debug and establish CPU/GPU Emulation environment Provide debug leadership, input to test plans and hands on execution Work with extended teams to debug environment, drive cross team testing (Firmware, Software, Diags/tools, Validation, Apps) Triage failures with design, verification, firmware, software, and emulation teams Research and enable new tools and infrastructure to support emulation activities Run and collect data for analysis on AMD s high-end emulators and simulation models Develop scripts/tools to parse data from emulation runs Instrument firmware code to support failure debug Run and collect functional and performance data for HPC workloads Attend weekly meetings, status communication, presentations. SKILLS AND EXPERIENCE REQUIREMENT Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning) Debugging experience is a must particularly in HW/SW co-debug environments Ability to trace code across multiple domains and root cause using waveforms and other tracing tools Understanding of Verilog, VHDL design Understanding of System Verilog, UVM verification environments is a plus Knowledge of computer hardware architecture (Graphic card, CPU/APU, memory, bus logic, and display technologies) Knowledge of memories (LPDDR5, HBM3/4, SPI, etc) and Bus arch (PCIe, CXL, AMBA, DFI, etc) Knowledge of computer software architecture and boot flow (bootrom, firmware, bios, device drivers, OS) Knowledge of secure platform concepts such as Root of Trust, Chain of Trust, FW signing, encryption Knowledge of platform management HW and SW components such as BMC, SMC and board management software libraries Knowledge of HPC, Parallel programming (OpenMP, OpenMPI), heterogeneous platforms consisting of CPU and GPU a plus Working knowledge of Linux/Unix environment and shell scripting Experience in Building and Installing software packages on Linux platform a plus Programming skills, C, C++, Python, Tcl, Ruby, assembly (ARM & x86) Familiarity with bug tracking tools such as Jira Excellent oral and written communication skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in electrical / electronics or computer engineering with 10+Yrs of exp

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 15+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering