Orchestrate the functional validation of CPU Cores by participating in the Test plan definition, Content generation, Execution and Debug of critical functional issues. Isolate and triage generic system level failures into a more focused area of the platform or CPU. Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Cores Validation team in program meetings providing status to program management PREFERRED EXPERIENCE: Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) x86 assembly programming Debug techniques and methodologies Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion ACADEMIC CREDENTIALS: Masters degree in CS/EE with 10-20 years of experience.

You are a self-starter who is able to achieve successful outcomes in a non-hierarchical environment. Detailed oriented , you have the ability to multitask through planning/organizing. You have excellent communication and presentation skills and a passion to push the limits of software on innovative platforms . KEY RESPONSIBILITIES: Performance analysis and software optimization Build and deploy software for the most advanced HPC (High Performance Compute) , data science, Virtualization , and machine learning platforms in the worl d Define/develop/execute regression test models and track the results Driv e innovation in production software environment s Combine advanced software engineering skills with a drive to explore novel approaches to solve important problems in heterogeneous computing at the large scales Evaluate and review of existing processes and continuously strive to optimize the workflow PREFERRED EXPERIENCE: (3 to 15 years) Good understanding of test lifecycle, QA process & terminology. Strong knowledge of Device drivers, graphics, multimedia, Codec. Test Execution Experience in an automation lab with multiple systems. Define, develop, execute functional/performance/load tests, and integrate them with automated test systems. Establishing and sharing best practices, designing, and executing a robust test strategy. Proficiency in at least one programming language preferably Python. Strong understanding & Hands-on exp. with Linux OS internals, device manager. Hands-on issue debugging skills, issue isolation with Linux kernel, driver module level. Strong understanding of PC hardware, SoC, Chipsets, Graphics cards, BIOS & VBIOS. Understanding of parallel programming, ideally OpenCL, ROCm, CUDA, and OpenACC is a plus. Understanding machine learning, artificial intelligence, computer vision technologies is a plus. Strong analysis, problem-solving & interpersonal skills. Good verbal & written communication skill is a must. Good attitude, result-driven & ability to deliver on next-gen technology. ACADEMIC CREDENTIALS: B achelors or Masters degree in Electrical Engineering, Mathematics, Computer Science, Engineering, or an equivalent

You are a self-starter who is able to achieve successful outcomes in a non-hierarchical environment. Detailed oriented , you have the ability to multitask through planning/organizing. You have excellent communication and presentation skills and a passion to push the limits of software on innovative platforms . KEY RESPONSIBILITIES: Performance analysis and software optimization Build and deploy software for the most advanced HPC (High Performance Compute) , data science, Virtualization , and machine learning platforms in the worl d Define/develop/execute regression test models and track the results Driv e innovation in production software environment s Combine advanced software engineering skills with a drive to explore novel approaches to solve important problems in heterogeneous computing at the large scales Evaluate and review of existing processes and continuously strive to optimize the workflow PREFERRED EXPERIENCE: Extensive C++ experience, preferably in production environments Prior experience of scripting with Perl, Python, Shell, TCL/TK, and AutoIT is an added advantage Knowledge of Windows and Linux environments Experience with software development process and tools such as debuggers and source code control systems a plus Knowledge of KVM/XEN/VMWARE is a plus ACADEMIC CREDENTIALS: B achelors or Masters degree in Electrical Engineering, Mathematics, Computer Science, Engineering, or an equivalent

Performance analysis and software optimization Build and deploy software for the most advanced HPC (High Performance Compute) , data science, Virtualization , and machine learning platforms in the worl d Define/develop/execute regression test models and track the results Driv e innovation in production software environment s Combine advanced software engineering skills with a drive to explore novel approaches to solve important problems in heterogeneous computing at the large scales Evaluate and review of existing processes and continuously strive to optimize the workflow PREFERRED EXPERIENCE: (3 to 15 years) Good understanding of test lifecycle, QA process & terminology. Strong knowledge of Device drivers, graphics, multimedia, Codec. Test Execution Experience in an automation lab with multiple systems. Define, develop, execute functional/performance/load tests, and integrate them with automated test systems. Establishing and sharing best practices, designing, and executing a robust test strategy. Proficiency in at least one programming language preferably Python. Strong understanding & Hands-on exp. with Linux OS internals, device manager. Hands-on issue debugging skills, issue isolation with Linux kernel, driver module level. Strong understanding of PC hardware, SoC, Chipsets, Graphics cards, BIOS & VBIOS. Understanding of parallel programming, ideally OpenCL, ROCm, CUDA, and OpenACC is a plus. Understanding machine learning, artificial intelligence, computer vision technologies is a plus. Strong analysis, problem-solving & interpersonal skills. Good verbal & written communication skill is a must. Good attitude, result-driven & ability to deliver on next-gen technology. ACADEMIC CREDENTIALS: B achelors or Masters degree in Electrical Engineering, Mathematics, Computer Science, Engineering, or an equivalent

Lead amdgpu kernel-mode GPU driver enhancements for AMD graphics products. Oversee driver bring-up, qualification, and performance optimization on new hardware. Resolve complex customer and QA-reported issues, implementing preventive measures. Foster partnerships and strategic collaboration with the open-source graphics community. As an SMTS, you would still be involved in individual contribution but with an increased focus on team leadership and strategic decision-making. PREFERRED EXPERIENCE: 12+ years of experience developing system software and kernel mode drivers for Linux and derivatives . Extensive expertise in graphical system programming, Linux ecosystem, and open-source development practices. Strong C programming skills, understanding of graphics systems software, and knowledge of computer architecture and operating systems. Proven experience leading and mentoring teams, driving technical projects, and collaborating with cross-functional teams. Ways to stand out from the crowd: Experience working in the Linux DRM/KGD (Direct Rendering Manager / Kernel Graphics Driver) subsystem . Track record of open-source contributions, strategic collaborations, and active involvement in the graphics development community. ACADEMIC CREDENTIALS: Bachelors or M asters degree (preferred) in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

1. Must have SoC implementation knowledge with deep level expertise in at least one domain. 2. Have responsibility for processes of significant technical importance and for results in SoC implementation and/OR related areas. 3. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation. 4. Influences technical decisions that have a significant impact on final product. 5. Requires limited supervision and is evaluated according to project performance. 6. Coaches and mentors less experienced staff; influences others as a technical leader. 7. very good communication and presentation skills 8. Proficiency in scripting Required Skills: 1. SoC implementation expertise. Multi million gates integration. 2. Low power implementation, Constraints validation, Formal verification 3. Floorplanning, Power planning. 4. Clock Tree Synthesis (CTS). 5. Awareness of Synthesis, SCAN and DFT implementation 6. Static Timing analysis (STA). 7. Analysis: IR, EM, Noise. 8. Physical Verification

Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partne rs PREFERRED EXPERIENCE: Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Windows, Linux and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Motivating leader with good interpersonal skills ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

The Release Operations Developer reports to the manager in the Release Management team. Release Manager, in DevOps, is responsible for scheduling, planning, and controlling the softwares development and delivery process. As a Release Operations Developer, you will be responsible for interacting with the Development teams to make them deliver the services on time and will co-ordinate with both IT operations and developers. You will be responsible helping the Release Manager in the Release Management lifecycle that involves the stages such as scheduling the release, coordinating between teams, and deployment of release as per the schedule. As Release Operations Developer, you will have to co-ordinate the release after completing the testing stage and deployment stage, and work closely with the application development team, testing team, and production team. You will have to maintain proper coordination between these teams to update the project related information. You need to ensure usage of release management tools to manage the release. Overall, you will be concerned with planning, testing, tracking, release, deployment, communication, and risk management. Roles and Responsibilities: Plan the release of project deliverables and release life cycle. Communicate the project-related tasks, such as plans, timelines, requirements, etc., between different teams. Coordinate the release schedule and resources required depending upon the third-party applications, defect backlogs, planned releases, and infrastructure updates. Track the progress and find issues, if any. Always work to improve the process of release. Make sure that the release is planned according to the release schedule. Schedule the release readiness reviews before deployment and milestone reviews after each release. Create plans for the implementation and deployment as per the release schedule. Plan and give weekly updates on the release activities Help the Release Manager to lead the Go-Live activities to deploy the software successfully. Team up with relevant development teams responsible for building the automation tools used to develop and deploy the software. Involve in the CAB meetings to discuss the release schedules with the team and find roadblocks, if any. Maintain documentation related to procedures on build and release, various notifications lists, and dependencies. Make improvements in the methodologies used for configuration management and development of software that helps to find ways to use in configuration management. Skills and qualifications: B.Tech in Computer Science or an equivalent degree Project management experience Atleast 5 years of relevant experience in working with DevOps and Agile methodologies Working knowledge of Software Development Lifecycle Expertise in computer programming Team management skills Experience using Application Release Automation tools Knowledge of traditional agile methodologies, including Scrum, Waterfall, or Kanban Good understanding of application infrastructure, system architecture, and operating system

Ensure issues are solved on time with quality. Lead complex debug efforts for internal Silicon findings to identify root cause and resolution. Manage and track technical issues, risks and priorities. Manage customer and executive communications, including program status, risks and opportunities. Publish debug program indicators to identify major roadblocks and drive changes to improve debug throughput. Evaluate at the end of every program milestone if the open issues are gating to go to the next milestone. Drive improvements to the debug process based on the program learnings. Preferred Skills: 15+ years or more of experience in validation roles involving debugging OS, FW, Silicon, and HW issues. Understanding of PC industry standard busses and their software stack, such as PCIe, CXL. Strong knowledge of X86 architecture, SoC design, memory, RAS & power management Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, Device Drivers and System BIOS interactions. Excellent communication and coordination skill1. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Experience in Technical program management. A thorough understanding of datacenter industry technologies and their software stack.

AMD is seeking a Platform Emulation Engineer to join our Data Center GPU organization. Our products support the rapidly scaling Data Center and High-Performance Compute infrastructure. You will be an integral member of the Platform emulation team responsible for emulation infrastructure development, execution and debug of critical firmware used in our HPC and ML products, developing test plans and execute test cases to enhance silicon test coverage, train and support validation teams on emulation technology, build and execute industry standard HPC benchmarks and applications on the emulator. As a platform emulation engineer you will have an opportunity to work on bleeding edge SoC architecture and technology and participate in development of emulation infrastructure to enable pre-silicon activities to ensure high quality Silicon and fast time to market. You will work alongside our team of innovative engineers to support the deployment of AMD s Instinct ML products targeting Supercomputers and Data Center workloads. KEY RESPONSIBILITIES CPU/GPU Firmware/OS bring up and debug using leading edge emulators (Veloce, Zebu, Palladium) Develop/modify/enhance functional/stress tests to find silicon bugs on emulator Validate features in firmware including but not limited to RAS, Resets, Power management, Secure boot, ethernet networking, Virtualization and Confidential Compute. Validate multi-socket configurations in emulation using firmware Bring up the full AMD graphics software stack in emulation Bring up ML/AI applications in emulation Collaborate with workloads and SW teams, run apps in multi-socket configurations, collect and interpret results for debug and tuning Checkout of IP features in software simulation model as a pre-step for emulation Interface with Central Emulation team responsible for helping to develop, debug and establish CPU/GPU Emulation environment Provide debug leadership, input to test plans and hands on execution Work with extended teams to debug environment, drive cross team testing (Firmware, Software, Diags/tools, Validation, Apps) Triage failures with design, verification, firmware, software, and emulation teams Research and enable new tools and infrastructure to support emulation activities Run and collect data for analysis on AMD s high-end emulators and simulation models Develop scripts/tools to parse data from emulation runs Instrument firmware code to support failure debug Run and collect functional and performance data for HPC workloads Attend weekly meetings, status communication, presentations. SKILLS AND EXPERIENCE REQUIREMENT Experience of secure platform concepts such as Root of Trust, Chain of Trust, FW signing, encryption . Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning) Debugging experience is a must particularly in HW/SW co-debug environments Ability to trace code across multiple domains and root cause using waveforms and other tracing tools Understanding of Verilog, VHDL design Understanding of System Verilog, UVM verification environments is a plus Knowledge of computer hardware architecture (Graphic card, CPU/APU, memory, bus logic, and display technologies) Knowledge of memories (LPDDR5, HBM3/4, SPI, etc) and Bus arch (PCIe, CXL, AMBA, DFI, Ethernet MII etc.) Knowledge of computer software architecture and boot flow (bootrom, firmware, bios, device drivers, OS) Knowledge of platform management HW and SW components such as BMC, SMC and board management software libraries Knowledge of HPC, Parallel programming (OpenMP, OpenMPI), heterogeneous platforms consisting of CPU and GPU a plus Working knowledge of Linux/Unix environment and shell scripting Experience in Building and Installing software packages on Linux platform a plus Programming skills, C, C++, Python, Tcl, Ruby, assembly (ARM & x86) Familiarity with bug tracking tools such as Jira Excellent oral and written communication skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in electrical / electronics or computer engineering with around 5+Yrs of exp

AMD is seeking a Platform Emulation Engineer to join our Data Center GPU organization. Our products support the rapidly scaling Data Center and High-Performance Compute infrastructure. You will be an integral member of the Platform emulation team responsible for emulation infrastructure development, execution and debug of critical firmware used in our HPC and ML products, developing test plans and execute test cases to enhance silicon test coverage, train and support validation teams on emulation technology, build and execute industry standard HPC benchmarks and applications on the emulator. As a platform emulation engineer you will have an opportunity to work on bleeding edge SoC architecture and technology and participate in development of emulation infrastructure to enable pre-silicon activities to ensure high quality Silicon and fast time to market. You will work alongside our team of innovative engineers to support the deployment of AMD s Instinct ML products targeting Supercomputers and Data Center workloads. KEY RESPONSIBILITIES CPU/GPU Firmware/OS bring up and debug using leading edge emulators (Veloce, Zebu, Palladium) Develop/modify/enhance functional/stress tests to find silicon bugs on emulator Validate features in firmware including but not limited to RAS, Resets, Power management, Secure boot, ethernet networking, Virtualization and Confidential Compute. Validate multi-socket configurations in emulation using firmware Bring up the full AMD graphics software stack in emulation Bring up ML/AI applications in emulation Collaborate with workloads and SW teams, run apps in multi-socket configurations, collect and interpret results for debug and tuning Checkout of IP features in software simulation model as a pre-step for emulation Interface with Central Emulation team responsible for helping to develop, debug and establish CPU/GPU Emulation environment Provide debug leadership, input to test plans and hands on execution Work with extended teams to debug environment, drive cross team testing (Firmware, Software, Diags/tools, Validation, Apps) Triage failures with design, verification, firmware, software, and emulation teams Research and enable new tools and infrastructure to support emulation activities Run and collect data for analysis on AMD s high-end emulators and simulation models Develop scripts/tools to parse data from emulation runs Instrument firmware code to support failure debug Run and collect functional and performance data for HPC workloads Attend weekly meetings, status communication, presentations. SKILLS AND EXPERIENCE REQUIREMENT Experience of secure platform concepts such as Root of Trust, Chain of Trust, FW signing, encryption . Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning) Debugging experience is a must particularly in HW/SW co-debug environments Ability to trace code across multiple domains and root cause using waveforms and other tracing tools Understanding of Verilog, VHDL design Understanding of System Verilog, UVM verification environments is a plus Knowledge of computer hardware architecture (Graphic card, CPU/APU, memory, bus logic, and display technologies) Knowledge of memories (LPDDR5, HBM3/4, SPI, etc) and Bus arch (PCIe, CXL, AMBA, DFI, Ethernet MII etc.) Knowledge of computer software architecture and boot flow (bootrom, firmware, bios, device drivers, OS) Knowledge of platform management HW and SW components such as BMC, SMC and board management software libraries Knowledge of HPC, Parallel programming (OpenMP, OpenMPI), heterogeneous platforms consisting of CPU and GPU a plus Working knowledge of Linux/Unix environment and shell scripting Experience in Building and Installing software packages on Linux platform a plus Programming skills, C, C++, Python, Tcl, Ruby, assembly (ARM & x86) Familiarity with bug tracking tools such as Jira Excellent oral and written communication skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in electrical / electronics or computer engineering with 10+Yrs of exp

As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have minimum 8 to 15 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer/Electronics/Electrical Engineering with 5+Yrs of exp

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification Specifying design verification plan at SOC level Specifying or reviewing verification plans for complex blocks within the ASIC Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements Performing thorough coverage analysis to ensure design completeness Automating verification processes to improve efficiency Contributing to the development of new verification methodologies and tools Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes : o self-checking, reusable, automated verification environment : both at full-chip & block level o Constrained random generators and reference models PREFERRED EXPERIENCE: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering Minimum 6+ years of experience in ASIC Design Verification Must have excellent knowledge of ASIC Design Flow and SOC architecture Experience in developing complex testbench/model in verilog, System verilog or SystemC Experience with coverage-based verification methodology Experience in writing testplans and testcases Excellent debug skills in functional simulations are must. Experience in random test generation, coverage analysis, failure debug Strong Verilog, SystemVerilog, PLI interface, C/C++, Perl/Shell scripts programming skills. Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Must have good communication skills and the ability/desire to foster a team environment. Experience in PCIE and USB protocols verification Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have Exposure to leadership or mentorship is an asse t ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for a dynamic, upbeat software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD s abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for S oftware engineering development , and is diligent and passionate about Technology . KEY RESPONSIBILITIES: Validate new SW features before releasing them to customers Contribute to a high-functioning feature team C ollaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results PREFERRED EXPERIENCE: BS or MS in CS, EE or CE with 3+ years of software development experience Background in EDA tools development preferred Strong background in computer algorithms and data structures, especially graph algorithms Strong background in C++ programming including boost and STL Proficiency in scripting using Python and/or Perl Excellent problem-solving skills and willingness to think outside the box Experience with production software quality assurance practices, methodologies and procedures Excellent communication skills and experience working with global teams ACADEMIC CREDENTIALS: Bachelor s or Master s degree in Computer/Software Engineering, Computer Science, or related technical discipline

As the one of the design leads of the Programmable Clock & Methodologies team in India for AMDs Adaptive-Embedded Computing products, you will be responsible for driving the development of clocking solutions that meet the high standards of AMDs AECG products. This will involve leading a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office, inventing and implementing original solutions, addressing challenging clock problems in some of the industry s largest and most complex SOCs. Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional Architecture, Programable fabric, Integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology. THE PERSON: You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems. KEY RESPONSIBILITIES: Lead floor-planning, placement, routing, custom clock tree design, and optimization. Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power and IO planning Perform all aspects of design flow from feasibility analysis, logic synthesis, FP, place and route, FEV, power, timing, quality checks, and design closure. Collaborate with design, Physical design, IT/infrastructure teams to ensure successful CAD flow all the way from IP design to SoC/3DIC design. Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMDs next generation of programmable product families. Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing. Deep analysis of timing paths to identify and debug key issues. Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs. PREFERRED EXPERIENCE: You should have a deep understanding of clocking methodologies and experience in leading teams to deliver complex projects. Working knowledge of Programable clocking is a plus. Strong working knowledge in all aspects of Physical Design and Advanced Packaging (Professional Experience: 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs). You should be an expert in the development of clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met. Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis). Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus. Working experience of Package level Clock SIPI is a plus. Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.Defined timing/SDC and placement constraints for IPs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection. Familiarity with Verilog and system Verilog for design. Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to junior team members to help them develop their skills and advance their careers. ACADEMIC CREDENTIALS: Bachelor or master degree in computer engineering/Electronics or Electrical Engineering with 8-12+ years of exp.

Understanding of IP/SS/SoC Power Management(PM) techniques. Converting PM Specification to UPF Perform low power quality checks VSI/VCLP Debugging experience on Power aware simulation (NLP sim) Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including UPF, verification, Power sequence, and post-silicon bring-up Need to understand clocking, reset and soc top level topology changes to make connectivity as per the topology across Ips. Need to understand the requirements of power domain(power architecture) to write UPFs. Collaborate with architects, DV and PD engineers to understand the new features to group the logic into tiles based on functionality as well as PD FP requirements. Must have been expert with RTL coding and other Debug capabilities. Preferred Experience: 7+ years full-time experience in IP/SOC hardware design Experience doing ECOs Experience with power aware CDC runs Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Experience with RTL Quality Checks - Verilog lint tools (Spyglass), verilog simulation tools (VCS) and Clock domain crossing (CDC) tools Proficient in IP level ASIC or SoC level RTL integration work and verification Good understanding and hands-on experience in the Timing, UPF, CDC, RDC and other quality check concepts Proficient in debugging RTL code using quality check and simulation tools. Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills Exposure to leadership or mentorship is an asset. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

The candidate must have thorough knowledge of DFT basics such as DFT RTL insertion. scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Proficient in logic design using Verilog Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As a member of the G&E SoC DFT Team, the successful candidate will own the DFT RTL integration and MBIST responsibilities for the next gen of AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture MBIST/SMS Insertion at Tile/Block level MBIST/SMS Verification at Tile/Block levle and SoC level Experience in memory BIST architecture , memory repir and efuse Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer